Product data sheet. 2 of Philips Semiconductors. 74HC; 74HCT Dual retriggerable monostable multivibrator with reset. 3. Ordering information. 74HC Monostable Multivibrator are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for 74HC Monostable Multivibrator. DATA SHEET. Product specification. Supersedes data of September File under Integrated Circuits, IC Jul INTEGRATED CIRCUITS. 74HC/.
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The are dual retriggerable monostable multivibrators with output pulse width control by three methods: Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input na or the active HIGH-going edge input nb.
Alternatively an output delay can be terminated at any time by a LOW-going edge on input nrd, which also inhibits the triggering. An internal connection from nrd to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input nrd as shown in Table 3.
Schmitt-trigger action in the na and nb inputs, makes the circuit highly tolerant to slower input rise and fall times. Ordering information Table 1. Functional diagram Product data sheet Rev January of Logic symbol Fig 3. IEC logic symbol Fig 4.
Logic diagram Product data sheet Rev January of The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder datzsheet should remain floating or be connected to V CC.
Functional description Table 3. Limiting datashest Table 4. P tot derates linearly with 5. P tot derates linearly with 4. Product data sheet Rev January of Recommended operating conditions Table 5.
Dynamic characteristics Table 7. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. Measurement points are given in Table 8.
Propagation delays from inputs na, nb, nrd to outputs nq, nq and output transition times Product data sheet Rev January of Test circuit for measuring switching times Table 8. Timing component connections This output pulse can be eliminated using the circuit shown in Datasneet Power-up output pulse elimination circuit Product data sheet Rev January of When a system containing this device is powered-down or a rapid decrease of V CC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes.
To avoid this possibility, use a damping diode D EXT preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Figure Power-down protection circuit Product data sheet Rev January of Package outline Fig Revision history Table Power dissipation capacitance condition for 74HCT is corrected. Preliminary [short] data sheet Qualification This catasheet contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
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Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC will cause permanent damage to the device.
Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted.
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V All rights reserved. For more information, please visit: Datawheet and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use of current.
Features and benefits The is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors.
Ordering information The are 8-bit multiplexer with eight binary inputs I0 to I7three select inputs S0. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock CP. Ordering information The is a.
It decodes four binary weighted address inputs A0 to A3 to sixteen mutually. Ordering information The decodes three binary weighted address inputs A0, A1 and A2 to eight mutually exclusive. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs Dn. Ordering information The is a with a clock input CPan overriding asynchronous master reset. Ordering information The decodes two binary weighted address inputs na0, na1 to four mutually exclusive outputs.
General description The is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs. The outputs are fully buffered for the highest noise.
General description The provides a single 3-input AND gate. The input can be driven from either 3.