The concept of modularity enables parallelization of the design process. Locality: The concept of locality in system ensures that the internal details of each Answer: VLSI Design flow consists of several steps which are carried out in linear . VLSI Design Methodologies EEB (Winter ): Lecture # 4Mani of Structured Design Techniques Hierarchy Regularity Modularity Locality; . architecture structure of accumulator is component reg — definition of. Digital VLSI Circuits. 1. Introduction to ASIC Design a. Design Strategies: Hierarchy, Regularity, Modularity & Locality b. Chip Design Options: Gate Array, Field.
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The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale systems design – in short, due to the advent of VLSI.
The number of applications of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power or, in other words, the intelligence of these applications is the driving force for the fast development of this field.
The current leading-edge technologies such as low bit-rate video and cellular communications already provide the end-users a certain amount of processing power and portability. This trend is expected to rregularity, with very important implications on VLSI and systems design.
One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth in order to handle real-time video, for example. The level of integration as measured by the number of logic gates in a monolithic chip has been steadily rising for almost three lovality, mainly due to the rapid progress in processing technology and interconnect technology.
Here, the numbers for circuit complexity should be interpreted only as representative examples to show the order-of-magnitude. A logic block can contain anywhere from 10 to transistors, depending on the function.
The most important message here is that the logic complexity per chip has been and still is increasing exponentially. The monolithic integration of a large regulzrity of functions on a single chip usually provides:. Therefore, the current trend of integration will also continue in the foreseeable future.
Advances in device manufacturing technology, and especially the steady reduction of minimum feature size minimum length of a transistor or an interconnect realizable on chip support this trend.
At that time, a minimum feature size of 0.
The actual development of the technology, however, has far exceeded these expectations. A minimum size of 0. As a direct result of this, the integration density has also exceeded previous expectations – the first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available bypushing the envelope of integration density. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips.
It can be observed that in terms of transistor count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular and thus more cells can be integrated with much less area for interconnects. Generally speaking, logic chips such as microprocessor chips and digital signal processing DSP chips contain not only large arrays of memory SRAM cells, but also many different functional units.
As a result, their design complexity is considered much higher than that of memory chips, although advanced memory chips contain some sophisticated logic functions. The design complexity of logic chips increases almost exponentially with the number of transistors to be integrated. This is translated into the increase in the design cycle time, which is the time period from the start of the chip development until the mask-tape delivery time.
However, in order to make the best use of the current technology, the chip development time has to be short enough to allow the maturing of chip manufacturing and timely delivery to customers. As a result, the level of actual logic integration tends to fall short of the integration level achievable with the current processing technology. Sophisticated computer-aided design CAD tools and methodologies are developed and applied in order to manage the rapidly increasing design complexity.
The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then the revision of requirements and its impact analysis must be considered. The Y-chart first introduced by D.
Gajski shown in Fig. The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floorplanning. The next design evolution in the behavioral domain defines finite state machines FSMs which are structurally implemented with functional modules such as registers and arithmetic logic units ALUs.
These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnects area and signal delays.
The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use. Note that the verification of design plays a very important role in every step during this process.
The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market. Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow.
Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated.
Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels bottom up as early as possible.
In the following, we will examine design methodologies and structured approaches which have been developed over the years to deal with both complex hardware and software projects. Regardless of the actual size of the project, the basic principles of structured design will improve the prospects of success.
Some of the classical techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality. This approach is very similar to the software case where large programs are split into smaller and smaller sections until simple subroutines, with well-defined functions and interfaces, can be written. Correspondingly, a hierarchy structure can be described in each domain separately.
However, it is important for the simplicity of design that localit hierarchies in different domains can be mapped into each other easily. As an example of structural hierarchy, Fig.
The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates. At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of the hierarchy. In the physical domain, partitioning a complex system midularity its various functional blocks will provide a valuable guidance for the actual realization of these blocks on chip.
Obviously, the approximate reguularity and size area of each sub-module should be estimated in order to provide a useful floorplan. This physical view describes the external geometry of the adder, the locations of input and output pins, and how pin locations allow some signals in this case the carry signals to be transferred from one sub-block to the other without external routing. At lower levels of the physical hierarchy, the internal mask. Note that there is a corresponding physical description for every module in the structural hierarchy, i.
The hierarchical design approach reduces the design complexity by dividing the large system into several sub-modules. Usually, other design concepts and design approaches are also needed to simplify the process.
Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. A good example of regularity is the design of array structures consisting of identical modu,arity – such as a parallel multiplication array. Regularity can exist at all levels of abstraction: At the transistor level, uniformly sized transistors simplify the design. At the logic level, identical gate structures can be used, etc. Note that all of these circuits were designed by using inverters and tri-state buffers only.
If the designer has a small library of well-defined and well-characterized basic building blocks, a number of different functions can cojcept constructed by using this principle.
Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces.
Modularity allows that each block or module can be designed relatively independently from each other, since there is no ambiguity about the function and the signal interface of these blocks. All of the blocks can be combined with ease at the end of the design process, to form the large system. The concept of modularity enables the parallelisation of the design process. It also allows the use of generic modules in various designs – the well-defined functionality and signal interface allow plug-and-play design.
By defining well-characterized interfaces for each module in the system, we effectively ensure that the internals of each module become unimportant to the exterior modules. Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible.
This last point is extremely important for avoiding excessive interconnect delays. Time-critical operations should be performed locally, without the need to access distant modules or signals.
If necessary, the replication of some logic may solve this problem in large system architectures. Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the functionality at low cost.
Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality.
This design style provides a means for fast prototyping and also for cost-effective chip design, especially for low-volume applications. The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors.
A more detailed view showing the locations of switch matrices used for interconnect routing is given in Fig. The LUT is a digital memory that stores the truth table of the Boolean function.
Thus, it can generate any function of up to four variables or any two functions of three variables. The control terminals of multiplexers are not shown explicitly in Fig.
The CLB is configured such that many different logic functions can be realized by programming its array. More sophisticated CLBs have also been introduced to map complex functions.